Office of Commercialization Published Technologies
A Spatial Multi-bit Time-Domain Matrix Multiplier Interface for Approximate Computing

A Spatial Multi-bit Time-Domain Matrix Multiplier Interface for Approximate Computing

Description:

Challenge: Lack of energy efficient and compact MAC units

Large scale parallel implementation of matrix multiply and accumulate (MAC) cores poses significant energy and area constraints in the analog voltage domain under reduced supply voltage.  A scalable alternative for this complex design is required for various approximate computing applications.

 

The Technology: Multi-bit time-domain matrix for approximate computing

This is a spatial multi-bit sub 1-V time-domain matrix multiplier interface using multi-bit back-gate-driven delay elements.  Novel architecture performs matrix MAC computations using time-domain signal processing with resistive weights at a sub-1 supply of 0.7V.  A time-to-digital converter is also integrated for quantization.  A prototype is fabricated in 65nm CMOS technology and occupies active area of 0.04 mm2.  Tested applications include image recognition using machine learning for handwritten digits.

 

Applications:

•       All complex microprocessor chips.

•       DSP applications include filtering, convolution, and inner products.

•       Several shift and add operations and cryptography applications.

 

Advantages:

•   Resultant energy per MAC computation is about 15x lower than a digital CMOS combinational based parallel-tree MAC.

•       Compact layout in a reduced chip area.

 

Intellectual Property Protection:

US Provisional Patent Application Filed

Patent Information: