Office of Commercialization Published Technologies
NP-Separate VLSI Design Methodology

NP-Separate VLSI Design Methodology


Challenge:  Fixed functionality of standard cell designs

Use of existing standard cell libraries in very-large-scale integration (VLSI) design enables short time to market for complex microprocessor chips.  Standard cells mix both NFETs and PFETs.  Because components within cells vary in size, neither space nor resultant function is optimized for all uses.  Standardized building blocks offer limited options to fine-tune overall system performance, and do not allow for optimal selection of transistors within each cell.


The Technology:  Method to use only NFETs or PFETs in each cell

A new design methodology, NP-Separate, minimizes layout area of a given design.  NP-Separate uses N cells and P cells composed exclusively of NFETs or PFETs.  All the NFETs in an N cell or all the PFETs in a P cell have the same width.  Simulated NP-Separate cells demonstrate cutsize reductions of 19% and wirelength reductions of 14%



•       All complex microprocessor chips.

•       Personal computers, cell phones, digital camera, and other electronics.



•       Customization not restrained by standard cell libraries.

•       More compact cell layouts.


Intellectual Property Protection:

Filed US Provisional Patent Application


Patent Information: