Network-on-Chip (NoC) Hardware Accelerators Abstract: This patented technology describes various configurations of Networks-on-Chip (NoCs), such as those with multiple wired and wireless links and dynamic node allocation. In some embodiments, a torus interconnect structure is employed. Advantages: Reduced network latency by offering multiple alternative communication nodes. Increased throughput. Intellectual Property Protection: Issued Patent, US 9,608,684 Learn More Karin Biggs Technology Licensing Associate Washington State University (509) 335-3553 karin.biggs@wsu.edu Reference No: 1334-OIPA-OC Bookmark this page Download as PDF Inventors Partha Pande Anantharaman Kalyanaraman Turbo Majumder Key Words