Network-on-Chip (NoC) Hardware Accelerators


This patented technology describes various configurations of Networks-on-Chip (NoCs), such as those with multiple wired and wireless links and dynamic node allocation.  In some embodiments, a torus interconnect structure is employed.



Reduced network latency by offering multiple alternative communication nodes.

Increased throughput.


Intellectual Property Protection:

Issued Patent, US 9,608,684

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Eric Wannamaker
Technology Licensing Associate
Washington State University
(509) 335-5004
Reference No: 1334-OIPA-OC


Partha Pande
Anantharaman Kalyanaraman
Turbo Majumder

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