Search Results - partha+pande

3 Results Sort By:
Small-World Network-on-Chip (SWNoC) Routing Methods and Systems
Abstract: Millimeter(mm)-wave wireless Small-World NoC (SWNoC) is an enabling interconnect architecture to design high performance and low power multicore chips. SWNoC has an overall irregular topology, making it important to design suitable deadlock-free routing mechanisms. This technology incorporates irregular network routing strategies. Tested...
Published: 5/25/2023   |   Inventor(s): Partha Pande, Deuk Heo
Network-on-Chip (NoC) Hardware Accelerators
Abstract: This patented technology describes various configurations of Networks-on-Chip (NoCs), such as those with multiple wired and wireless links and dynamic node allocation. In some embodiments, a torus interconnect structure is employed. Advantages: Reduced network latency by offering multiple alternative communication nodes. Increased...
Published: 5/25/2023   |   Inventor(s): Partha Pande, Anantharaman Kalyanaraman, Turbo Majumder
Network-on-Chip (NoC) Systems with Wireless Interconnects
Abstract: This is an enabling technology to design energy efficient and high bandwidth multicore architectures with improved thermal profile over conventional wireline. Evaluation yielded lower latency and energy dissipation compared to a conventional wireline mesh. Network-on-chip (NoC) or network-on-a-chip is a communication subsystem on an...
Published: 6/9/2023   |   Inventor(s): Partha Pande